The half-bridge circuit shown in FIG. 1A has two n-channel MOS-transistors T and B, whose drain-source-paths are connected to form a series circuit. This series circuit is connected to a supply voltage Vcc and to a reference potential GND. A control circuit 1 is provided for driving the MOS-transistors B and T. The control circuit 1 is connected to the gate terminals TG and BG of the MOS-transistors T and B, to the supply voltage Vcc, as well as to the reference potential GND for supply purposes. A bootstrap supply-circuit provides a bootstrap supply-voltage Vbts to the control circuit 1 in order to enable the control circuit 1 to generate a control-signal TG_ex with a potential high enough to drive the gate of the top MOS-transistor T of the half-bridge 2 which operates as a high side switch. The junction between the top MOS-transistor T and the bottom (i.e. the low-side) MOS-transistor B forms a phase-terminal PHASE which a complex impedance load circuit 3 is connected to. The bootstrap supply circuit BTS, as well as the load circuit 3 are not important for the following considerations and are not explained in further detail.
The control-signals TG_ex and BG_ex provided by the control circuit 1 and received by the gate-terminals TG, BG of the top transistor T and the bottom MOS-transistor B respectively are driven dependent on the input-signal PWM received by the input-terminal IN of the control circuit 1.
The internal logic of the control circuit 1 ensures a proper switching of the half-bridge 2.
FIG. 1b shows an exemplary timing diagram of the input-signal PWM, the control-signals BG_ex and TG_ex and the phase-signal PH which can be regarded as an output signal of the half-bridge. As can be seen from FIG. 1b the phase-signal PH merely follows the input-signal PWM. A rising edge in the input-signal PWM is followed by a rising edge in the phase-signal PH after a delay time T_delay. In order to switch the phase-signal from a low into a high state, after a rising edge in the input-signal PWM, the bottom (low-side) transistor B has to be switched off and then the top (high-side) transistor T has to be switched on.
The phase-signal PH will go to a high state not earlier than a low resistance channel has formed in the gate region of the top transistor T. The forming of a low resistance channel in a MOS-transistor happens a short delay time T_g after the control-signal applied to the gate terminal of the transistor has switched to a high state. This delay time T_g corresponds to a delay time of a low-pass formed of the bonding resistance and the gate-source-capacitance of each MOS-transistor. For this reason one has to distinguish between an external control-signal (e.g. TG_ex, BG_ex) applied to an external gate terminal of a transistor and an “internal” control-signal (e.g. TG_in, BG_in) representing the actual gate voltage on the chip.
The aforementioned delay time T_delay is mainly determined by the delays of the internal switching logic and the delay time T_g between the external control-signal TG_ex, BG_ex and the internal control-signal TG_in, BG_in. In order to ensure an optimal switching process the time T_wait between a falling edge of the signal BG_ex controlling the gate of the bottom transistor B and a rising edge of the signal TG_ex controlling the gate of the top transistor T should be minimized.
But the delay time T_wait can not be set arbitrarily small. If the external control-signal TG_ex of the top transistor T would be switched to a high level immediately after the control-signal BG_ex of the bottom transistor was switched to a low level the internal control-signals TG_in and BG_in would overlap and an unwanted cross-conduction between the top transistor T and the bottom transistor B would occur. Cross-conduction implicates a large power dissipation which can lead to a thermal destruction of the half-bridge.
To avoid these adverse effects of cross-conduction conventional driver circuits guarantee a fixed delay T_wait between two corresponding edges of the control-signal BG_ex and TG_ex, such that the corresponding internal control-signals TG_in and BG_in will not overlap and cross-conduction is inhibited. Since the delay T_g between the internal and the external control-signals can vary with temperature the fixed delay time T_wait could be too high or too small for operation in certain temperature ranges. This problem is usually solved by employing sensing means for sensing the cross-conduction current and adapting the delay time T_wait between an edge of the control-signal BG_ex and a corresponding edge of the control-signal TG_ex, such that cross conduction is reduced to a minimum. This conventional solution has the disadvantage, that additional sensing means for sensing the cross-conduction current and an additional input pin for the control circuit is necessary.